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LPC2470FET208 Datasheet(PDF) 30 Page - NXP Semiconductors |
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LPC2470FET208 Datasheet(HTML) 30 Page - NXP Semiconductors |
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30 / 89 page  LPC2470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 14 February 2011 30 of 89 NXP Semiconductors LPC2470 Flashless 16-bit/32-bit microcontroller – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048, 4096, and 8192 row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2470 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. 7.7.1 Features • Two DMA channels. Each channel can support a unidirectional transfer. • The GPDMA can transfer data between the 16 kB SRAM, external memory, and peripherals such as the SD/MMC, two SSPs, and the I2S interface. • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first. • AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface. |
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