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LPC1227FBD64301 Datasheet(PDF) 48 Page - NXP Semiconductors

Part No. LPC1227FBD64301
Description  32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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LPC1227FBD64301 Datasheet(HTML) 48 Page - NXP Semiconductors

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LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 21 February 2011
48 of 60
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
11.5 SSP/SPI interface
[1]
Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V; VDD(IO) = 3.0 V to 3.6 V.
[3]
Tcy(clk) = 12  Tcy(PCLK).
[4]
Tamb = 25 C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V.
Table 16.
Dynamic characteristics: SSP pins in SPI mode
Tamb =25 C.
Symbol
Parameter
Conditions
Min
Max
Unit
Tcy(clk)
clock cycle time
when only
transmitting
[1]
<tbd>
-
ns
when only
receiving
<tbd>
-
SSP master
tDS
data set-up time
in SPI mode
[2]
15
-
ns
tDH
data hold time
in SPI mode
[2]
0-
ns
tv(Q)
data output valid time
in SPI mode
[2]
-10
ns
th(Q)
data output hold time
in SPI mode
[2]
0-
ns
SSP slave
tDS
data set-up time
in SPI mode
[3][4]
0-
ns
tDH
data hold time
in SPI mode
[3][4]
3
 T
cy(PCLK) + 4
-
ns
tv(Q)
data output valid time
in SPI mode
[3][4]
-3
 T
cy(PCLK) + 11
ns
th(Q)
data output hold time
in SPI mode
[3][4]
-2
 T
cy(PCLK) + 5
ns


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