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LPC1227FBD64301 Datasheet(PDF) 35 Page - NXP Semiconductors |
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LPC1227FBD64301 Datasheet(HTML) 35 Page - NXP Semiconductors |
35 / 60 page LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 — 21 February 2011 35 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD(3V3) for different system clock frequencies Conditions: VDD(3V3) = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. Fig 7. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (peripherals disabled) <tbd> X (X) XX X XX X 001aab173 X X X X X X (X) X 12 MHz 4 MHz 1 MHz 33 MHz 24 MHz 002aag023 temperature ( °C) −40 85 35 10 60 −15 4 12 8 16 IDD (mA) 0 |
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