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LPC1227FBD64301 Datasheet(PDF) 18 Page - NXP Semiconductors

Part No. LPC1227FBD64301
Description  32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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LPC1227FBD64301 Datasheet(HTML) 18 Page - NXP Semiconductors

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LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 21 February 2011
18 of 60
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
In the LPC122x, the NVIC supports 32 vectored interrupts. In addition, up to 12 of the
individual GPIO inputs are NVIC-vector capable.
Four programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation.
Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral
interrupts. The NMI is not available on an external pin.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 55 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, a rising edge or falling edge, or both.
7.6 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.6.1 Features
Programmable pull-up resistor.
Programmable digital glitch filter.
Programmable input inverter.
Programmable drive current.
Programmable open-drain mode.
7.7 Micro DMA controller
The micro DMA controller enables memory-to-memory, memory-to-peripheral, and
peripheral-to-memory data transfers. The supported peripherals are: UART0 (transmit
and receive), UART1 (transmit and receive), SSP/SPI (transmit and receive), ADC, RTC,
32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match
output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit
counter/timer 1 (match output channel 0), comparator 0, comparator 1, GPIO0 to GPIO2.
7.7.1 Features
Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit
data bus.
21 DMA channels.
Handshake signals and priority level programmable for each channel.
Each priority level arbitrates using a fixed priority that is determined by the DMA
channel number.


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