FMP1617DAx

CMOS LPRAM

Revision 0.4

Jul. 2010

9

LOW POWER MODES

1. Mode Register Set

A19 ~ A5

A4

A3

A2

A1

A0

0

ZZ

Enable/Disable

Array On/Off

on /ZZ

Half Selection

Array Refresh Area

/ZZ Enable/Disable

A4

Type

0

Deep Power Down Enable

1

DPD Disable (Default)

Array On/Off on /ZZ

A3

Type

0

Partial Array Refresh Mode (Default)

1

Reduced Memory Size Mode

Note: If the register is written to enable the Deep

Power Down, the part will go into Deep Power Down

during the following time that /ZZ is driven low and

there is no MRS update. When /ZZ is driven high, all

of the register settings will return to default state for

the part (i.e. full array refresh, Deep Power Down

Disabled).

Note: The RMS(Reduced Memory Size) mode is enabled after

/ZZ goes high and remains enabled after /ZZ goes high. To

change to a different mode, the mode register will have to be

rewritten.

Half Selection (Top / Bottom)

A2

Type

0

Bottom (Default)

1

Top

Array Refresh Area

A1

A0

Type

0

0

Full Array (Default)

01

RFU

10

½ Array

11

¼ Array

2. MRS Update

Address

/CS

/UB, /LB

/WE

tWC

tWR(4)

tBW

tWP(1)

tCW(2)

tAS(3)

tAW

/ZZ

tZZWE

Register Write Start

Register Write

Complete

Register Update

Complete

The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any

updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a

don’t care When /ZZ is low during the register updates.