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F81865 Datasheet(PDF) 34 Page - Feature Integration Technology Inc. |
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F81865 Datasheet(HTML) 34 Page - Feature Integration Technology Inc. |
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34 / 128 page  F81865 May, 2010 V0.28P 34 R -------------------------- PCN ( Drive 0 ) ------------------------ R -------------------------- PCN ( Drive 0 ) ------------------------ R |------------------ SRT -------------------| |------------------ HUT -------------------| R |------------------------------------- SRT ---------------------------------------| ND R -------------------------- SC/EOT ------------------------ R LOCK 0 D3 D2 D1 D0 GAP WGATE R 0 EIS EFIFO POLL |---------------- FIFOTHR ---------------| R ---------------------------- PRETRK -------------------------- Sense Drive Status Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark Command W 0 0 0 0 0 1 0 0 Command code W 0 0 0 0 0 HDS DS1 DS0 Result R ---------------------------- ST3 -------------------------- Status information abut disk drive Invalid Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark Command W ---------------------------- Invalid Codes -------------------------- FDC goes to standby state. Result R ---------------------------- ST0-------------------------- ST0 = 80h 7.3. UART The F81865 provides up to 6 UART ports and supports IRQ sharing for system application. The UARTs are used to convert data between parallel format and serial format. They convert parallel data into serial format on transmission and serial format into parallel data on receiver side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. They have FIFO mode to reduce the number of interrupts presented to the host. Both receiver and transmitter have a 16-byte FIFO. The below content is about the UARTs device register descriptions. All the registers are for software porting reference. Receiver Buffer Register ⎯ Base + 0 Bit Name R/W Default Description 7-0 RBR R 00h The data received. Read only when LCR[7] is 0 |
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