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CY14B101LA Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY14B101LA
Description  1-Mbit (128 K 횞 8/64 K 횞 16) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B101LA Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY14B101LA
CY14B101NA
Document #: 001-42879 Rev. *K
Page 4 of 26
Figure 3. 48-Ball FBGA and 54-Pin TSOP II
Table 1. Pin Definitions
Pin Name
I/O Type
Description
A0 – A16
Input
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for x8 configuration.
A0 – A15
Address inputs. Used to select one of the 65,536 words of the nvSRAM for x16 configuration.
DQ0 – DQ7
Input/Output
Bidirectional data I/O lines for ×8 configuration. Used as input or output lines depending on operation.
DQ0 – DQ15
Bidirectional Data I/O Lines for ×16 configuration. Used as input or output lines depending on operation.
WE
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power
supply
Power supply inputs to the device. 3.0 V +20%, –10%
HSB[8]
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
Power
supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvol-
atile elements.
NC
No connect No connect. This pin is not connected to the die.
Pinouts (continued)
NC
DQ7
DQ6
DQ5
DQ4
VCC
DQ3
DQ2
DQ1
DQ0
NC
A0
A1
A2
A3
A4
A5
A6
A7
VCAP
WE
A8
A10
A11
A12
A13
A14
A15
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(not to scale)
OE
CE
VCC
NC
VSS
NC
A9
NC
NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
(x16)
[6]
[7]
[4]
[5]
WE
VCC
A11
A10
VCAP
A6
A0
A3
CE
NC
NC
DQ0
A4
A5
NC
DQ2
DQ3
NC
VSS
A9
A8
OE
VSS
A7
NC
NC
NC
NC
A2
A1
NC
VCC
DQ4
NC
DQ5
DQ6
NC
DQ7
NC
A15
A14
A13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A16
NC
NC
DQ1
48-FBGA
(not to scale)
Top View
(x8)
[6]
[4]
[5]
[+] Feedback


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