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ADSP-BF533SBBC-5V Datasheet(PDF) 14 Page - Analog Devices |
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ADSP-BF533SBBC-5V Datasheet(HTML) 14 Page - Analog Devices |
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14 / 64 page  Rev. H | Page 14 of 64 | January 2011 ADSP-BF531/ADSP-BF532/ADSP-BF533 As shown in Figure 9, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 0.5 to 64 multiplica- tion factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios. The maximum frequency of the system clock is fSCLK. The divi- sor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynami- cally without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). When the SSEL value is changed, it affects all of the peripherals that derive their clock signals from the SCLK signal. The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 7. This programmable core clock capability is useful for fast core frequency modifications. BOOTING MODES The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have two mechanisms (listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence. The BMODE pins of the reset configuration register, sampled during power-on resets and software-initiated resets, imple- ment the following modes: • Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). • Boot from 8-bit or 16-bit external flash memory – The flash boot routine located in boot ROM memory space is set up using asynchronous Memory Bank 0. All configuration set- tings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). • Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit addressable, or Atmel AT45DB041, AT45DB081, or AT45DB161) – The SPI uses the PF2 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit addressable EEPROM/flash device is detected, and begins clocking data into the processor at the beginning of L1 instruction memory. • Boot from SPI serial master – The Blackfin processor oper- ates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor asserts a GPIO pin, called host wait (HWAIT), to signal the host device not to send any Figure 9. Frequency Modification Methods Table 6. Example System Clock Ratios Signal Name SSEL3–0 Divider Ratio VCO/SCLK Example Frequency Ratios (MHz) VCO SCLK 0001 1:1 100 100 0101 5:1 400 80 1010 10:1 500 50 PLL 0.5 u to 64u ÷1 to 15 ÷1,2, 4, 8 VCO CLKIN “FINE” ADJUSTMENT REQUIRES PLL SEQUENCING “COARSE” ADJUSTMENT ON-THE-FLY CCLK SCLK SCLK d CCLK SCLK d 133 MHz Table 7. Core Clock Ratios Signal Name CSEL1–0 Divider Ratio VCO/CCLK Example Frequency Ratios (MHz) VCO CCLK 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 Table 8. Booting Modes BMODE1–0 Description 00 Execute from 16-bit external memory (bypass boot ROM) 01 Boot from 8-bit or 16-bit FLASH 10 Boot from serial master connected to SPI 11 Boot from serial slave EEPROM/flash (8-,16-, or 24- bit address range, or Atmel AT45DB041, AT45DB081, or AT45DB161serial flash) |
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