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ADSP-BF561SKBCZ-6V Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF561SKBCZ-6V Datasheet(HTML) 6 Page - Analog Devices |
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6 / 64 page  ADSP-BF561 flexible configuration and upgradability of system memory while allowing the core to view all SDRAM as a single, contigu ous, physical address space. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 64M byte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64M bytes of memory. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On- chip I/O devices have their control registers mapped into mem ory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired. Booting The ADSP-BF561 contains a small boot kernel, which config ures the appropriate peripheral for booting. If the ADSP-BF561 is configured to boot from boot ROM memory space, the pro cessor starts executing from the on-chip boot ROM. Event Handling The event controller on the ADSP-BF561 handles all asynchro nous and synchronous events to the processor. The ADSP-BF561 provides event handling that supports both nest ing and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servic ing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut down of the system. • Exceptions – Events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. Conditions such as data alignment violations or undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, and an explicit software instruction. Each event has an associated register to hold the return address and an associated “return from event” instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF561 event controller consists of two stages: the Core Event Controller (CEC) and the System Interrupt Control ler (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority inter rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF561. Table 1 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 1. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3 Exceptions EVX 4 Global Enable 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 System Interrupt Controller (SIC) The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by Rev. E | Page 6 of 64 | September 2009 |
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