8

8535F–SEEPR–6/10

Atmel AT25320B/640B

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-

segments can be protected. Any of the data within any selected segment will therefore be read only. The block

write protection levels and corresponding status register control bits are shown in Table 3-4 on page 8.

The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regu-

lar memory cells (e.g., WREN, t

The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the

Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit

is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device

is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the

block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that

are not block-protected.

Note:

When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low.

READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin requires the following

sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed

line should be driven high after the data comes out. The read sequence can be continued since the byte address is

automatically incremented and data will continue to be shifted out. When the highest address is reached, the

address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read

cycle.

Table 3-4.

Block Write Protect Bits

Level

Status Register Bits

Array Addresses Protected

BP1

BP0

Atmel AT25320B

Atmel AT25640B

0

0

0

None

None

1(1/4)

0

1

0C00

0FFF

1800

1FFF

2(1/2)

1

0

0800

0FFF

1000

1FFF

3(All)

1

1

0000

0FFF

0000

1FFF

Table 3-5.

WPEN Operation

WPEN

WP

WEN

Protected

Blocks

Unprotected

Blocks

Status

Register

0

X

0

Protected

Protected

Protected

0

X

1

Protected

Writeable

Writeable

1

Low

0

Protected

Protected

Protected

1

Low

1

Protected

Writeable

Protected

X

High

0

Protected

Protected

Protected

X

High

1

Protected

Writeable

Writeable