AT25128B datasheet(9/24 Pages) ATMEL | serial electrically-erasable programmable read only memory

Part No.	AT25128B

Description	serial electrically-erasable programmable read only memory

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Manufacturer	ATMEL [ATMEL Corporation]

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8698B–SEEPR–3/10

AT25128B/256B

WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be exe-

cuted. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction

may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected

address field location selected by the Block Write Protection Level. During an internal write cycle, all commands

will be ignored except the RDSR instruction.

A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write

op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see

Table 2-6 for the address key). Programming will start after the CS pin is brought high. (The Low-to-High transition

of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.

The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If

Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register

instruction is enabled during the Write programming cycle.

The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low

order address bits are internally incremented by one; the high order bits of the address will remain constant. If

more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be

overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write

cycle.

Note:

If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby

state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.

Table 3-6.

Address Key

Address

AT25128B

AT25256B

A

N

A

13 −A0

A

14 −A0

Don’t Care Bits

A

15 −A14

A

15

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