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AT25128B Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT25128B Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 24 page  8 8698B–SEEPR–3/10 AT25128B/256B WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory seg- ments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 2-4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the reg- ular memory cells (e.g. WREN, tWC, RDSR) Table 3-4. Block Write Protect Bits. The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 3-5. WPEN Operation READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address to be read (Table 2-6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incre- mented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. Level Status Register Bits Array Addresses Protected BP1 BP0 AT25128B AT25256B 0 0 0 None None 1 (1/4) 0 1 3000 – 3FFF 6000 – 7FFF 2 (1/2) 1 0 2000 – 3FFF 4000 – 7FFF 3 (All) 1 1 0000 – 3FFF 0000 – 7FFF WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable |
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