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IC-MD Datasheet(PDF) 20 Page - IC-Haus GmbH |
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IC-MD Datasheet(HTML) 20 Page - IC-Haus GmbH |
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20 / 23 page  preliminary preliminary iC-MD RS-422 QUADRATURE ENCODER RECEIVER/COUNTER WITH SPI AND BiSS Rev A1, Page 20/23 BiSS and SSI INTERFACE The BiSS interface is a bidirectional serial interface, which is used to read out the sensor data values and to write and read the internal configuration registers. For a detailed description of the protocol, see the BiSS C specification. It consist of 3 configurable channels: channel eata error warning data length CRC polynom CRC mode CH0 AB counter NERR NWARN 16 + 2 bit 1000011 inverted 24 + 2 bit 32 + 2 bit 48 + 2 bit SPI Channel NERR NSPICHVAL 16 + 2 bit 1000011 inverted 24 + 2 bit 32 + 2 bit 48 + 2 bit CH1 UPD NABERR NUPDVAL 24 + 2 bit 100101 inverted TP1 NABERR NTPVAL 24 + 2 bit 100101 inverted CH2 TP1 NABERR NTPVAL 24 + 2 bit 100101 inverted TP2 NABERR NTPVAL 24 + 2 bit 100101 inverted Notes channel 0 data length configurable via: CNTCFG (Adr.0x00, bit 3:0) Table 44: BiSS Channels The error (NERR) and warning (NWARN) bit of the channel 0 signal the same data to be output at the pins NERR and NWARN, it’s by default: NERR: ABERR (AB signal error) NWARN: UPDVAL (UPD Reg. up to date) This bits can also be configured like the NERR and NWARN outputs, with the registers MASK (table 40) and NMASK(table 41) Two different data can be selected for each chan- nel, register CHxSEL (table 45) selects the data to be transmitted by the channels. CHxSEL Addr. 0x04; bit (7,5,3) 000 Code Function XX0 channel 0: AB counter data XX1 channel 0: SPI data channel X0X channel 1: UPD data X1X channel 1: TP1 data 0XX channel 2: TP1 data 1XX channel 2: TP2 data Table 45: BiSS Channel Selection The three channel are enabled by default, but all of them can be disable with the registers NENCH0 (table 46) and ENCHx (table 47) NENCH0 Addr. 0x04; bit (2) 0 Code Function 0 BiSS channel 0 enabled 1 BiSS channel 0 disabled Table 46: Not Enable BiSS Channel 0 ENCHx Addr. 0x04; bit (6,4) 00 Code Function X0 BiSS channel 1 disabled 0X BiSS channel 2 disabled Table 47: Enable BiSS Channel 1 and 2 SSI Protocol An SSI protocol is selected if the input pin SLI is open. This enable signal has an internal digital filter of 5 µs. A clock pulse train from a controller is used to gate out sensor data. Between each clock pulse train there is a SSI timeout during which fresh data is moved into the register. Data is shifted out when the iC-MD receives a pulse train from the controller. When the least sig- |
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