IC-MD datasheet(16/23 Pages) ICHAUS

Part #	IC-MD

Description	ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

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Manufacturer	ICHAUS [IC-Haus GmbH]

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16 / 23 page

preliminary

iC-MD RS-422 QUADRATURE

ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

Rev A1, Page 16/23

ABERRx

Addr. 0x48, 0x49, 0x4A;

bit 7

Code

Description

0

No decodiﬁcation error in counter x

1

Decodiﬁcation error in counter x

Notes

x = 0, 1, 2

Reset by reading Adr. 0x48 (ABERR0), 0x49

(ABERR1) and 0x4A (ABERR2)

The corresponding counter must be reset (ABRES)

after an error

Table 27: AB Decodiﬁcation Error

The maximum counting range of the counters depends

on the counter conﬁguration (see table 16). A counter

with the bit length "n" has the maximum counting range

will be from -2n-1 up to 2n-1-1. The corresponding bit

OVFx is set to 1 if the counter exceeds these values.

OVFx

Addr. 0x48, 0x49, 0x4A;

bit 6

Code

Description

0

no overﬂow in counter x

1

overﬂow in counter x

Notes

x = 0, 1, 2

reset by reading Adr. 0x48 (OVF0), 0x49 (OVF1)

and 0x4A (OVF2)

Table 28: Counter Overﬂow Warning

ZEROx bits indicate that the counter value has

reached the zero value.

ZEROx

Addr. 0x48, 0x49, 0x4A;

bit 5

Code

Description

0

no zero of counter x

1

zero of counter x

Notes

x = 0, 1, 2

reset by reading Adr. 0x48 (ZERO0), 0x49

(ZERO1) and 0x4A (ZERO2)

Table 29: Zero Value in Counter x

If VDD reaches the power off supply level (VDDoff,

Spec. Item No. 602), the iC-MD is reset and the RAM

initialized to the default value. Status bit PDWN indi-

cates that this initialization has taken place.

PDWN

Addr. 0x48, 0x49, 0x4A;

bit 4

Code

Description

0

No undervoltage

1

Undervoltage

Notes

Reset by reading Adr. 0x48, 0x49 or 0x4A

Table 30: Undervoltage Reset

RVAL status bit indicates that the reference value was

load in the REF register, after the "Zero Codiﬁcation"

process. After power-on, this bit remains at 0 until the

second different Index pulse.

RVAL

Addr. 0x48; bit 3

Code

Description

0

REF Reg. not valid

1

REF Reg. valid

Notes

Reset by the instruction ZCEN(see table 23)

Table 31: REF Register Valid

Every time that the UPD register is loaded, the status

bit UPDVAL (UPD valid) is set to 1 until the status bit

UPD or the register UPD is read via SPI or BiSS.

UPDVAL

Addr. 0x48; bit 2

Code

Description

0

UPD Reg. not valid

1

UPD Reg. valid

Notes

Reset by reading Adr. 0x48 or the register UPD via

SPI (Adr. 0x0A) or BiSS (Channel 1)

Table 32: UPD Register Valid

If the number of AB edges between two index signals

is greater than 223-1=8388607 or lower than -223=-

8388608 the status bit OVFREF is set to 1 and indi-

cates that the value of the UPD and REF registers are

not valid.

OVFREF

Addr. 0x48; bit 1

Code

Description

0

No Overﬂow in reference counter

1

Overﬂow in reference counter

Notes

Reset by reading Adr. 0x48

Table 33: Reference Counter Overﬂow

After loading TP1/TP2 register, either via pin TPI or in-

struction TP (see table 24), the bit TPVAL is set to 1

and remains at 1 until the reading of TPVAL, TP1 or

TP2 via SPI or BiSS.

TPVAL

Addr. 0x48; bit 0

Code

Description

0

TPx registers not loaded

1

New value loaded in TPx

Notes

Reset by reading Adr. 0x48, register TP1 or register

TP2 via SPI (Adr. 0x0C and 0x0E) or BiSS

(channel 1 and channel 2, see table 45)

Table 34: Touch-Probe Valid

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