ADC1410S065 datasheet(22/35 Pages) NXP

Part #	ADC1410S065

Description	Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

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Manufacturer	NXP [NXP Semiconductors]

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22 / 35 page

ADC1410S065_080_105_125_2

Objective data sheet

Rev. 02 — 4 June 2009

22 of 35

NXP Semiconductors

ADC1410S065/080/105/125

Single 14-bit ADC 65, 80, 105 or 125 Msps

11.5.5 Digital offset

By default, the ADC1410S delivers output code that corresponds to the analog input.

However it is possible to add a digital offset to the output code via the SPI (bits

DIG_OFFSET; see Table 23).

11.5.6 Test patterns

For test purposes, the ADC1410S can be conﬁgured to transmit one of a number of

predeﬁned test patterns (via bits TESTPAT_SEL; see Table 24). A custom test pattern can

be deﬁned by the user (TESTPAT_USER; see Table 25 and Table 26) and is selected

when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the

analog input.

11.5.7 Output codes versus input voltage

Table 14.

Output codes

VINP − VINM

Offset binary

Two’s complement

OTR pin

<

−1

00 0000 0000 0000

10 0000 0000 0000

1

−1

00 0000 0000 0000

10 0000 0000 0000

0

−0.9998779

00 0000 0000 0001

10 0000 0000 0001

0

−0.9997559

00 0000 0000 0010

10 0000 0000 0010

0

−0.9996338

00 0000 0000 0011

10 0000 0000 0011

0

−0.9995117

00 0000 0000 0100

10 0000 0000 0100

0

....

0

−0.0002441

01 1111 1111 1110

11 1111 1111 1110

0

−0.0001221

01 1111 1111 1111

11 1111 1111 1111

0

10 0000 0000 0000

00 0000 0000 0000

0

+0.0001221

10 0000 0000 0001

00 0000 0000 0001

0

+0.0002441

10 0000 0000 0010

00 0000 0000 0010

0

....

0

+0.9995117

11 1111 1111 1011

01 1111 1111 1011

0

+0.9996338

11 1111 1111 1100

01 1111 1111 1100

0

+0.9997559

11 1111 1111 1101

01 1111 1111 1101

0

+0.9998779

11 1111 1111 1110

01 1111 1111 1110

0

+1

11 1111 1111 1111

01 1111 1111 1111

0

> +1

11 1111 1111 1111

01 1111 1111 1111

1

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