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STD100N3LF3 Datasheet(PDF) 4 Page - STMicroelectronics

Part No. STD100N3LF3
Description  N-channel 30 V, 0.0045 Ω, 80 A, DPAK planar STripFET™ II Power MOSFET
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STD100N3LF3 Datasheet(HTML) 4 Page - STMicroelectronics

 
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Electrical characteristics
STD100N3LF3
4/14
Doc ID 13206 Rev 3
2
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5.
On/off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown
voltage
ID = 250 µA, VGS = 0
30
V
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating @125 °C
1
10
µA
µA
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
±200
nA
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
1
2.5
V
RDS(on)
Static drain-source on
resistance
VGS = 10 V, ID = 40 A
VGS = 5 V, ID = 20 A
0.0045
0.008
0.0055
0.01
VGS = 10 V,
ID = 40 A @125 °C
VGS = 5 V,
ID = 20 A @125 °C
0.0068
0.0146
Table 6.
Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
gfs
(1)
1.
Pulsed: pulse duration=300µs, duty cycle 1.5%
Forward transconductance
VDS = 10 V, ID = 15 A
-
31
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f = 1 MHz,
VGS = 0
-
2060
728
67
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 24 V, ID = 80 A
VGS = 5 V
Figure 16 on page 9
-
20
7
7.5
27
nC
nC
nC
RG
Gate input resistance
f = 1 MHz gate DC Bias = 0
test signal level = 20 mV
open drain
-1.9


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