LPC1810 datasheet(2/84 Pages) NXP

Part #	LPC1810

Description	32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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2 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

2 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

Two PLLs allow CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. Second PLL can be used for USB.

Clock output.

Serial interfaces:

Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per

second total.

10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load.

One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip PHY.

One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support synchronous mode and a smart

card interface conforming to ISO7816 specification.

One C_CAN 2.0B controller with one channel.

Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1Mbit/s.

One standard I2C-bus interface with monitor mode and standard I/O pins.

One I2S interface with DMA support and with one input and one output.

Digital peripherals:

External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

LCD controller with DMA support and a programmable display resolution of up to

1024H

× 768V. Supports monochrome and color STN panels and TFT color panels;

supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.

SD/MMC card interface.

Eight-channel General-Purpose DMA (GPDMA) controller can access all memories

on the AHB and all DMA-capable AHB slaves.

Up to 80 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors and open-drain modes.

GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

State Configurable Timer (SCT) subsystem on AHB.

Four general-purpose timer/counters with capture and match capabilities.

One motor control PWM for three-phase motor control.

One Quadrature Encoder Interface (QEI).

Repetitive Interrupt timer (RI timer).

Windowed watchdog timer.

Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

Alarm timer; can be battery powered.

Analog peripherals:

One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

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