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LPC1850 Datasheet(PDF) 11 Page - NXP Semiconductors

Part # LPC1850
Description  32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1850 Datasheet(HTML) 11 Page - NXP Semiconductors

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LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 3 January 2011
11 of 84
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
P3_0[2]
F13
<tbd>
I/O
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
O
I2S_RX_MCLK — I2S receive master clock.
I/O
I2S_TX_SCK — I2S transmit clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
O
I2S_TX_MCLK — I2S transmit master clock.
P3_1[2]
G11
<tbd>
I/O
I2S_TX_WS — Transmit Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
I/O
I2S_RX_WS — Receive Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
I
CAN1_RD — CAN1 receiver input.
O
USB1_IND1 — USB1 port indicator LED control output 1.
P3_2[2]
F11
<tbd>
I/O
I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
O
CAN1_TD — CAN1 transmitter output.
O
USB1_IND0 — USB1 port indicator LED control output 0.
P3_3[2]
B14
<tbd>
-
n.c.
-n.c.
I/O
SSP0_SCK — Serial clock for SSP0.
O
SPIFI_SCK — Serial clock for SPIFI.
P3_4[2]
A15
I; PU
I/O
GPIO1[14] — General purpose digital input/output pin.
-n.c.
-n.c.
I/O
SPIFI_SIO3 — I/O lane 3 for SPIFI.
P3_5[2]
C12
I; PU
I/O
GPIO1[15] — General purpose digital input/output pin.
-n.c.
-n.c.
I/O
SPIFI_SIO2 — I/O lane 2 for SPIFI.
P3_6[2]
B13
I; PU
I/O
GPIO0[6] — General purpose digital input/output pin.
-n.c.
I/O
SSP0_SSEL — Slave Select for SSP0.
I/O
SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.
P3_7[2]
C11
<tbd>
-
n.c.
-n.c.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
I/O
SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
Table 3.
Pin description …continued
Symbol
Reset
state
[1]
Type Description


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