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PCF2119RU2DB2 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCF2119RU2DB2 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 83 page PCF2119X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 7 — 15 November 2010 8 of 83 NXP Semiconductors PCF2119x LCD controllers/drivers 8. Functional description 8.1 Oscillator and timing generator The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency fclk which equals either the built in oscillator frequency fosc or an external clock frequency fclk(ext). 8.1.1 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.1.2 Internal clock To use the on-chip oscillator, pin OSC must be connected to VDD1. The on-chip oscillator provides the clock signal for the display system. No external components are required. 8.1.3 External clock If an external clock will be used, the input is at pin OSC. The resulting display frame frequency is given by: (1) Remark: Only in the power-down mode the clock is allowed to be stopped (pin OSC connected to VSS), otherwise the LCD is frozen in a DC state, which is not suitable for the liquid crystals. 8.2 Reset function and Power-On Reset (POR) The PCF2119x must be reset externally when power is turned on. If no external reset is performed, the chip might start-up in an unwanted state. For the external reset, pin POR has to be active HIGH. The reset has to be active for at least 3 oscillator periods in order for the reset to be executed. If the internal oscillator is used, the minimum reset activity time follows from the lowest possible oscillator frequency (fosc = 140 kHz, Tosc ~71 μs, 3 × Tosc ~215 μs). The internal oscillator start-up time is 200 μs (typ) up to 300 μs (max) after power-on. In case that an external oscillator is used, Tosc is dependent from fosc(ext). Afterwards the chip executes the Clear_display instruction, which requires 165 oscillator cycles. After the reset the chip has the state shown in Table 4 and is then ready for use. f fr f osc 3072 ------------ = |
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