DS2408

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PIO Logic-State Register

The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers

command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as

STRB

PIO Logic State Register Bitmap

ADDR

b7

b6

b5

b4

b3

b2

b1

b0

0088h

P7

P6

P5

P4

P3

P2

P1

P0

This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in

Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds

reading the first (least significant) bit of this register. See the Read PIO Registers command description

for details.

PIO Output Latch State Register

The data in this register represents the latest data written to the PIO through the Channel-access Write

command. This register is read using the Read PIO Registers command. Reading this register does not

hit.

PIO Output Latch State Register Bitmap

ADDR

b7

b6

b5

b4

b3

b2

b1

b0

0089h

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

This register is read-only. Each bit is associated with the output latch of the respective PIO channel as

shown in Figure 6.

The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO

channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU

supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that

RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).

PIO Activity Latch State Register

The data in this register represents the current state of the PIO activity latches. This register is read using

the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even

PIO Activity Latch State Register Bitmap

ADDR

b7

b6

b5

b4

b3

b2

b1

b0

008Ah

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as

shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin

command.