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MPC8572ELPXARLD Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc |
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MPC8572ELPXARLD Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 45 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 22. 4-Wire AC-Coupled SGMII Serial Link Connection Example Change in VOS between “0” and “1” VOS —— 25 mV — Output current on short to GND ISA, ISB —— 40 mA — Note: 1. This will not align to DC-coupled SGMII. XVDD_SRDS2-Typ=1.1 V. 2. |VOD| = |VSD2_TXn - VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|. 3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8572E’s SerDes 2 Control Register: •The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default); •The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. 4. VOS is also referred to as output common mode voltage. • 5.The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS2-Typ=1.1V, no common mode offset variation (VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n]. Table 37. SGMII DC Transmitter Electrical Characteristics (continued) Parameter Symbol Min Typ Max Unit Notes Δ MPC8572E SGMII SerDes Interface 50 Ω 50 Ω Transmitter SD2_TXn SD_RXm SD2_TXn SD_RXm Receiver CTX CTX 50 Ω 50 Ω SD2_RXn SD2_RXn Receiver Transmitter SD_TXm SD_TXm CTX CTX 50 Ω 50 Ω 50 Ω 50 Ω |
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