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MPC8572ELVTAVND Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc |
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MPC8572ELVTAVND Datasheet(HTML) 75 Page - Freescale Semiconductor, Inc |
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75 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 75 High-Speed Serial Interfaces (HSSI) of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in Section 15.2.1, “SerDes Reference Clock Receiver Characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 45 shows the SerDes reference clock input requirement for DC-coupled connection scheme. — For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND_SRDSn). Figure 46 shows the SerDes reference clock input requirement for AC-coupled connection scheme. • Single-ended Mode — The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. —The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 47 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use. Figure 45. Differential Reference Clock Input DC Requirements (External DC-Coupled) SD n_REF_CLK SD n_REF_CLK Vmax < 800 mV Vmin > 0V 100 mV < Vcm < 400 mV 200mV < Input Amplitude or Differential Peak < 800 mV |
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