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908E624 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc |
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908E624 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc |
18 / 40 page Analog Integrated Circuit Device Data 18 Freescale Semiconductor 908E624 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high side outputs. Other ports are also provided, which include a current sense operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I/O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details, refer to the 68HC908EY16 data sheet. PORT B I/O TERMINALS (PTB1:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details, refer to the 68HC908EY16 data sheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details, refer to the 68HC908EY16 data sheet. PORT D I/O TERMINALS (PTD:0:1) PTD1/TACH1 and PTD0/TACH0/BEMF are special- function, bidirectional I/O port terminals that can also be programmed to be timer terminals. For details, refer to the 68HC908EY16 data sheet. PORT E I/O TERMINAL (PTE1) PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details, refer to the 68HC908EY16 data sheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details, refer to the 68HC908EY16 data sheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details, refer to the 68HC908EY16 data sheet. |
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