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MCM63F837 Datasheet(PDF) 19 Page - Motorola, Inc |
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MCM63F837 Datasheet(HTML) 19 Page - Motorola, Inc |
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19 / 28 page  MCM63F837 •MCM63F919 19 MOTOROLA FAST SRAM SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1–1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using a 3.3 V tolerant logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TRST should be tied low and TCK, TDI, and TMS should be pulled through a resistor to 3.3 V. TDO should be left unconnected. TAP DC OPERATING CHARACTERISTICS (TA = 0 to 70°C, Unless Otherwise Noted) Parameter Symbol Min Max Unit Notes Input Logic Low VIL1 –0.5 0.8 V Input Logic High VIH1 2 3.6 V Input Leakage Current Ilkg — ±10 µA 1 Output Logic Low VOL1 — 0.4 V 2 Output Logic High VOH1 2.4 — V NOTES: 1. 0 V ≤ Vin ≤ VDDQ for all logic input pins. 2. For VOL = 0.4 V, 14 mA ≤ IOL ≤ 28 mA. TAP AC OPERATING CONDITIONS AND CHARACTERISTICS (TA = 0 to 70°C, Unless Otherwise Noted) AC TEST CONDITIONS Parameter Value Unit Input Timing Reference Level 1.5 V Input Pulse Levels 0 to 3.0 V Input Rise/Fall Time (20% to 80%) 1 V/ns Output Timing Reference Level 1.5 V Output Load (See Figure 1 Unless Otherwise Noted) — — Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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