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MCM63F837 Datasheet(PDF) 9 Page - Motorola, Inc

Part No. MCM63F837
Description  256K x 36 and 512K x 18 Bit Flow?밫hrough BurstRAM Synchronous Fast Static RAM
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCM63F837 Datasheet(HTML) 9 Page - Motorola, Inc

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MCM63F837
•MCM63F919
9
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 Through 5)
Next Cycle
Address
Used
SE1
SE2
SE3
ADSP
ADSC
ADV
G 3
DQx
Write 2, 4
Deselect
None
1
X
X
X
0
X
X
High–Z
X
Deselect
None
0
X
1
0
X
X
X
High–Z
X
Deselect
None
0
0
X
0
X
X
X
High–Z
X
Deselect
None
X
X
1
1
0
X
X
High–Z
X
Deselect
None
X
0
X
1
0
X
X
High–Z
X
Begin Read
External
0
1
0
0
X
X
0
High–Z
X
Begin Read
External
0
1
0
1
0
X
0
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES:
1. X = don’t care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
G
I/O Status
Read
L
L
Data Out (DQx)
Read
L
H
High–Z
Write
L
X
High–Z
Deselected
L
X
High–Z
Sleep
H
X
High–Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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