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MC9328MX21CJM Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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MC9328MX21CJM Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
49 / 100 page Specifications MC9328MX21 Technical Data, Rev. 3.4 Freescale Semiconductor 49 Figure 40. SDRAM Refresh Timing Diagram Table 32. SDRAM Write Cycle Timing Parameter Ref No. Parameter 1.8 V ± 0.1 V 3.0 V ± 0.3 V Unit Minimum Maximum Minimum Maximum 1 SDRAM clock high-level width 3.00 – 3 – ns 2 SDRAM clock low-level width 3.00 – 3 – ns 3 SDRAM clock cycle time 7.5 – 7.5 – ns 4 Address setup time 3.67 – 2 – ns 5 Address hold time 2.95 – 2 – ns 6 Precharge cycle period1 1. Precharge cycle timing is included in the write timing diagram. tRP2 2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual. –tRP2 –ns 7 Active to read/write command delay tRCD2 –tRCD2 –ns 8 Data setup time 3.41 – 2 – ns 9 Data hold time 2.45 – 2 – ns SDCLK CS CAS WE RAS ADDR DQ DQM BA 3 4 6 1 2 5 7 ROW/BA 7 |
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