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IR3508MTRPBF Datasheet(PDF) 11 Page - International Rectifier |
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IR3508MTRPBF Datasheet(HTML) 11 Page - International Rectifier |
11 / 19 page IR3508 Page 11 of 19 October 27, 2008 share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing the output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition. IR3508 THEORY OF OPERATION Block Diagram The Block diagram of the IR3508 is shown in Figure 5, and specific features are discussed in the following sections. + - + - CLK D Q + - + - VCC S R Q EAIN + - LGND IOUT GATEL PGND BOOST GATEH CSIN+ VCCL CSIN- PHSIN CLKIN DACIN PHSOUT SW RMPOUT PWM RESET VCC CALIBRATION CALIBRATION DACIN CALIBRATION CSAOUT DEBUG OFF SHARE_ADJ PHSIN DACIN DACIN-SHARE_ADJ VCCL IROSC IROSC CURRENT SENSE AMPLIFIER BODY BRAKING COMPARATOR PWM COMPARATOR PWM LATCH SHARE ADJUST AMPLIFIER - 1V X32.5 + OVP COMPARATOR GATEL NON- OVERLAP COMPARATOR 1V SYNCHRONOUS RECTIFICATION DISABLE COMPARATOR + PWM RAMP GENERATOR GATEL NON- OVERLAP LATCH GATEH NON- OVERLAP LATCH GATEL DRIVER GATEH DRIVER SET DOMINANT X 0.75 DEBUG COMPARATOR SET DOMINANT 0.8V (LOW=OPEN) RESET DOMINANT 0.15V GATEH NON- OVERLAP COMPARATOR NEGATIVE CURRENT COMPARATOR 100mV PWMQ 200mV (CLKIN for 1-PHASE) CLK D Q VCCL PHSIN . . . PSI_SYNC CLK D Q CLK D Q Q U183 DFFRSH . . . . . CLK D Q PSI_SYNC PHASE DELAY DFF 8CLK EAIN VCCL 500K ANTI-BIAS LATCH + - PSI 510mV 610mV CLK D Q 1V RESET DOMINANT + PSI COMPARATOR S R Q NEGATIVE CURRENT LATCH VCCL EAIN 3K + - S R Q + - PSI_SYNC PWM_CLK PSI_SYNC Figure 5: Block diagram Tri-State Gate Drivers The gate drivers are design to provide a 2A source and sink peak current (Bottom gate driver can sink 4A). An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot- through current and minimizing body diode conduction. The non-overlap latch is added to eliminate erroneous triggering caused by the switching noise. A fault condition is communicated to the phase IC via the control IC’s error amplifier without an additional dedicated signal line. The error amplifier’s output is driven low in response to any fault condition detected by the controller, such as VCCL under voltage or output overload, disabling the phase IC and activating Body BrakingTM. The IR3508 Body BrakingTM comparator detects the low signal at the EAIN and drives the bottom gate output low. This tri-state operation prevents negative inductor current and negative output voltage during power-down. A synchronous rectification disable comparator is used to detect the converter’s CSIN- pin voltage, which represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL is driven low, which disables synchronous rectification and eliminates negative current during power-up. |
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