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W83195CG-NP Datasheet(PDF) 14 Page - Winbond

Part # W83195CG-NP
Description  Winbond Clock Generator
Download  23 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W83195CG-NP Datasheet(HTML) 14 Page - Winbond

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W83195CG-NP
FOR INTEL NAPA PLATFORM
- 10 -
7.6 Register 5: ( Default : 00h )
BIT
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
DRI_CONT
(Reserved)
0
CPUT / SRCT / PCI_EXP / DOT96_T output state
in during POWER DOWN assertion.
1: Driven
(2*Iref)
0: Tristate (Floating)
CPUT / SRCT / PCI_EXP / DOT96_T output state
in during STOP Mode assertion.
1: Driven
(6*Iref)
0: Tristate (Floating)
Complementary parts always tri-state (floating) in
power down or stop mode.
R/W
6
Reserved
0
Reserved
R/W
5
Reserved
0
Reserved
R/W
4
Reserved
0
Reserved
R/W
3
Reserved
0
Reserved
R/W
2
Reserved
0
Reserved
R/W
1
Reserved
0
Reserved
R/W
0
SEL_ITP
0
Power on latched value of ITP_EN/PCICLK_F0 pin.
SRCCLK/CPU_ITP output clock selection :
1: CPU_ITP clock output
0: SRCCLK clock output
R/W
7.7 Register 6: ( Default : XXh )
BIT
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
Reserved
1
6
Reserved
0
5
Reserved
0
4
Reserved
0
Reserved
R/W
3
PCI/SRCCLK_STOP
1
To stop all PCICLK and SRCCLK output
1: Disable
0: Enable
R/W
2
FSC_BACK
X
Power on latched value of FSC pin.
R
1
FSB_BACK
X
Power on latched value of FSB pin.
R
0
FSA_BACK
X
Power on latched value of FSA pin.
R


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