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MAX5621 Datasheet(PDF) 11 Page - Maxim Integrated Products

Part No. MAX5621
Description  16-Bit DACs with 16-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5621 Datasheet(HTML) 11 Page - Maxim Integrated Products

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16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
______________________________________________________________________________________
11
Modes of Operation
The MAX5621/MAX5622/MAX5623 feature three modes
of operation:
Sequence mode
Immediate update mode
Burst mode
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 16 SHAs. At each SRAM
address location, the stored 16-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 16 SHAs (20µs per channel). Using an exter-
nal sequencer clock the update process takes 128
clock cycles (eight clock cycles per channel).
Immediate Update Mode
Immediate update mode is used to change the con-
tents of a single SRAM location, and update the corre-
sponding SHA output. In immediate update mode, the
selected output is updated before the sequencer
resumes operation. Select immediate update mode by
driving either IMMED or C1 high.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completed transparent to the serial bus activity. The
SRAM location of the addressed channel is then modi-
fied with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
This operation can take up to two cycles of the
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
being refreshed. Under conditions of extremely frequent
immediate updates (i.e., 1000 successive updates),
unacceptable droop can result.
Figure 5 shows an example of an immediate update
operation. In this example, data for channel 12 is
loaded while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other chan-
nels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an fSEQ period (if
any) has expired, channel 12 is updated to the new
data. Once channel 12 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
Burst Mode
Burst mode allows multiple SRAM locations to be
loaded at high speed. During burst mode, the output
voltages are not updated until the data burst is com-
plete and control returns to the sequencer. Select burst
mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer
resumes scrolling at the interrupted SRAM address.
New values are updated when their turn comes up in
the sequence.
After burst mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
UPDATE MODE
UPDATE TIME
Immediate update mode
2/fSEQ
Burst mode
33/fSEQ
Table 3. Update Mode
7
12
3
SKIP
12
7
8
9
24-BIT
WORD
CS
DIN
CHANNEL 12
UPDATED
INTERRUPTED
CHANNEL REFRESHED
2/fSEQ
LOAD ADDRESS 12
SHA ARRAY
UPDATE
SEQUENCE
Figure 5. Immediate Update Mode Timing Example


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