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MAX5621 Datasheet(PDF) 10 Page - Maxim Integrated Products

Part No. MAX5621
Description  16-Bit DACs with 16-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5621 Datasheet(HTML) 10 Page - Maxim Integrated Products

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16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
10
______________________________________________________________________________________
The resistive voltage-divider formed by the output resis-
tor (RO) and the load impedance (RL), scales the out-
put voltage. Determine VOUT_ as follows:
Ground Sense
The MAX5621/MAX5622/MAX5623 include a ground-
sense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
Output Clamp
The MAX5621/MAX5622/MAX5623 clamp the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
The clamping diodes allow the MAX5621/MAX5622/
MAX5623 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamping,
connect CH to VDD and CL to VSS, setting the clamping
voltages beyond the maximum output voltage range.
Serial Interface
The MAX5621/MAX5622/MAX5623 are controlled by an
SPI/QSPI/MICROWIRE-compatible 3-wire interface.
Serial data is clocked into the 24-bit shift register in an
MSB-first format, with the 16-bit DAC data preceding
the 4-bit SRAM address, required zero bit, 2-bit control,
and a fill 0 (Figure 4). The input word is framed by CS.
The first rising edge of SCLK after CS goes low clocks
in the MSB of the input word.
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data can be corrupted if CS is
not held low for an integer multiple of 24 bits.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching thresh-
old is compatible with TTL and most CMOS logic levels.
Serial Input Data Format and
Control Codes
The 24-bit serial input format, shown in Figure 4, compris-
es 16 data bits (D15–D0), 4 address bits (A3–A0), 1
required zero bit after the address bits, 2 control bits (C1,
C0), and a fill zero. The address code selects the output
channel as shown in Table 2. The control code configures
the device as follows:
1) If C1 = 1, immediate update mode is selected.
If C1 = 0, burst mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to main-
tain external input.
The operating modes can also be selected externally
through CLKSEL and IMMED. In the case where the
control bit in the serial word and the external signal
conflict, the signal that is a logic 1 is dominant.
VV
V
V
V
CH
OUT
CL
+
() ≥≥ ()
07
07
..
_
Scaling Factor
R
RR
V
V
scaling factor
L
LO
OUT
CHOLD
=
+
_
DATA
ADDRESS
CONTROL
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01
D0
A3
A2
A1
A0
0
C1
C0
0
MSB
LSB
Figure 4. Input Word Sequence
A3
A2
A1
A0
OUTPUT
0
0
0
0
OUT0 selected
0
0
0
1
OUT1 selected
0
0
1
0
OUT2 selected
0
0
1
1
OUT3 selected
0
1
0
0
OUT4 selected
0
1
0
1
OUT5 selected
0
1
1
0
OUT6 selected
0
1
1
1
OUT7 selected
1
0
0
0
OUT8 selected
1
0
0
1
OUT9 selected
1
0
1
0
OUT10 selected
1
0
1
1
OUT11 selected
1
1
0
0
OUT12 selected
1
1
0
1
OUT13 selected
1
1
1
0
OUT14 selected
1
1
1
1
OUT15 selected
Table 2. Channel/Output Selection


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