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MAX5621 Datasheet(PDF) 9 Page - Maxim Integrated Products

Part No. MAX5621
Description  16-Bit DACs with 16-Channel Sample-and-Hold Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5621 Datasheet(HTML) 9 Page - Maxim Integrated Products

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16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
_______________________________________________________________________________________
9
Detailed Description
Digital-to-Analog Converter
The MAX5621/MAX5622/MAX5623 16-bit digital-to-ana-
log converters (DACs) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
Sample-and-Hold Amplifiers
The MAX5621/MAX5622/MAX5623 contain 16 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. The MAX5621/MAX5622/MAX5623 provide a
very low 1mV/s droop rate.
Output
The MAX5621/MAX5622/MAX5623 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (IDD
and ISS). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the Absolute
Maximum Ratings.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see the Output Clamp section):
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
where code is the decimal value of the DAC input
code, VREF is the reference voltage, and VGS is the
voltage at the ground-sense input. With a 2.5V refer-
ence, the nominal end points are -4.0535V and
+9.0535V (Table 1). Note that these are “virtual” inter-
nal end-point voltages and cannot be reached with all
combinations of negative and positive power-supply
voltages. The nominal, usable DAC end-point codes for
the selected power supplies can be calculated as:
Lower end-point code = 32768 - ((2.5V - (VSS+0.75) /
200µV) (result
≥ 0)
Upper end-point code = 32768 + ((VDD - 2.4 - 2.5V) /
200µV) (result
≤ 65535)
V
code
V
V
OUT
REF
GS
= ⎛
⎝⎜
⎠⎟
××
×
() +
65535
5 2428
.
-
1.6214 VREF
VV
V
V
V
SS
OUT
DD
+
() ≤≤ ()
075
2 4
..
_
-
Table 1. Code Table
DAC INPUT CODE
MSB
LSB
NOMINAL OUTPUT
VOLTAGE (V)
VREF = +2.5V
1111 1111 1111 1111
9.0535
Full-scale output
1100 0111 0100 1010
6.15
Maximum output with VDD = 8.55V
1000 0000 0000 0000
2.5
Midscale output
0100 1111 0010 1100
0
VOUT_ = 0; all outputs default to this code after power-up
0010 1000 0001 1100
-2.0
Minimum output with VSS = -2.75V
0000 0000 0000 0000
-4.0535
Zero-scale output
Figure 3. Analog Block Diagram
GS
DAC
DATA
CH
OUT_
GAIN
AND
OFFSET
CHOLD
VREF
RO
ONE OF 16 SHA CHANNELS
16-BIT
DAC
RL
CL
AV = 1


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