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LDS3985PU15R Datasheet(PDF) 4 Page - STMicroelectronics |
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LDS3985PU15R Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 20 page Pin configuration LDS3985xx 4/20 Doc ID 11039 Rev 7 2 Pin configuration Figure 2. Pin connections (top view for SOT23-5L, top through view for DFN6) DFN6 SOT23-5L Table 2. Pin description Pin n° for SOT23-5L Pin n° for DFN6 Symbol Name and function 11 VI Input voltage of the LDO 2 5 GND Common ground 36 VINH Inhibit input voltage: on mode when VINH ≥ 1.2 V, off mode when VINH ≤ 0.4 V (Do not leave floating, not internally pulled down/up) 4 4 BYPASS Bypass pin: connect an external capacitor (usually 10 nF) to minimize noise voltage 53 VO Output voltage of the LDO - 2 N.C. Not connect |
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