450 datasheet(8/71 Pages) INTEL

Part #	450

Description	Celeron M Processor on 65 nm Process

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Manufacturer	INTEL [Intel Corporation]

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Introduction

8

Datasheet

bus, the address bus can deliver addresses two times per bus clock and is referred to

as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X

address bus provide a data bus bandwidth of up to 4.26 GB/second. The FSB uses

Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+

signaling technology with low power enhancements. The processor features the Auto

Halt, Stop Grant and Deep Sleep low power C-states.

The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-

FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package

technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero

Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket.

Celeron M processor supports the Execute Disable Bit capability. This feature combined

with a support operating system allows memory to be marked as executable or non

executable. If code attempts to run in non-executable memory the processor raises an

error to the operating system. This feature can prevent some classes of viruses or

worms that exploit buffer overrun vulnerabilities and can thus help improve the overall

security of the system. See the IA-32 Intel® Architecture Software Developer's Manual

for more detailed information.

1.1

Terminology

Term

Definition

#

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

XXXX means that the specification or value is yet to be determined.

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

AGTL+

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

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