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EP1AGX35EF484I6N Datasheet(PDF) 75 Page - Altera Corporation |
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EP1AGX35EF484I6N Datasheet(HTML) 75 Page - Altera Corporation |
75 / 234 page Chapter 2: Arria GX Architecture 2–69 PLLs and Clock Networks © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 Combined Resources Within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and eight regional clock lines. Multiplexers are used with these clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB (refer to Figure 2–57). You can use the Quartus II software to control whether a clock input pin drives either a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects the clocking resources if not specified. Figure 2–56. Dual-Regional Clocks Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network CLK[15..12] CLK[7..4] CLK[3..0] PLLs PLLs Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network CLK[15..12] CLK[7..4] CLK[3..0] Figure 2–57. Hierarchical Clock Networks Per Quadrant Clock [23..0] Column I/O Cell IO_CLK[7..0] Lab Row Clock [5..0] Row I/O Cell IO_CLK[7..0] Global Clock Network [15..0] Regional Clock Network [7..0] Clocks Available to a Quadrant or Half-Quadrant |
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