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EP1AGX35EF484I6N Datasheet(PDF) 64 Page - Altera Corporation |
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EP1AGX35EF484I6N Datasheet(HTML) 64 Page - Altera Corporation |
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64 / 234 page  2–58 Chapter 2: Arria GX Architecture Digital Signal Processing Block Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation f For more information about TriMatrix memory, refer to the TriMatrix Embedded Memory Blocks in Arria GX Devices chapter. Digital Signal Processing Block The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these use the multiplier as the fundamental building block. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Arria GX device has two to four columns of DSP blocks to efficiently implement DSP functions faster than ALM-based implementations. Each DSP block can be configured to support up to: ■ Eight 9 × 9-bit multipliers ■ Four 18 × 18-bit multipliers ■ One 36 × 36-bit multiplier L4 datain_a[56..42] byteena_a[5..4] dataout_a[59..48] L5 datain_a[71..57] byteena_a[7..6] dataout_a[71..60] R0 datain_b[14..0] byteena_b[1..0] dataout_b[11..0] R1 datain_b[29..15] byteena_b[3..2] dataout_b[23..12] R2 datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b dataout_b[35..24] R3 addressb[15..5] datain_b[41..36] dataout_b[47..36] R4 datain_b[56..42] byteena_b[5..4] dataout_b[59..48] R5 datain_b[71..57] byteena_b[7..6] dataout_b[71..60] Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2) Unit Interface Block Input Signals Output Signals |
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