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EP1AGX35EF484I6N Datasheet(PDF) 51 Page - Altera Corporation |
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EP1AGX35EF484I6N Datasheet(HTML) 51 Page - Altera Corporation |
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51 / 234 page  Chapter 2: Arria GX Architecture 2–45 MultiTrack Interconnect © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect. These column resources include: ■ Shared arithmetic chain interconnects in a LAB ■ Carry chain interconnects in a LAB and from LAB to LAB ■ Register chain interconnects in a LAB ■ C4 interconnects traversing a distance of four blocks in up and down direction ■ C16 column interconnects for high-speed vertical routing through the device Arria GX devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–40 shows shared arithmetic chain, carry chain, and register chain interconnects. Figure 2–39. R4 Interconnect Connections (Note 1), (2), (3) Notes to Figure 2–39: (1) C4 and C16 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. (3) The LABs in Figure 2–39 show the 16 possible logical outputs per LAB. Primary LAB (2) R4 Interconnect Driving Left Adjacent LAB can Drive onto Another LAB's R4 Interconnect C4 and C16 Column Interconnects (1) R4 Interconnect Driving Right LAB Neighbor LAB Neighbor |
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