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EP1AGX50CF484I6N Datasheet(PDF) 72 Page - Altera Corporation |
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EP1AGX50CF484I6N Datasheet(HTML) 72 Page - Altera Corporation |
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72 / 234 page  2–66 Chapter 2: Arria GX Architecture PLLs and Clock Networks Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation PLLs and Clock Networks Arria GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Global and Hierarchical Clocking Arria GX devices provide 16 dedicated global clock networks and 32 regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in Arria GX devices. There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device except the right side, as shown in Figure 2–54 and Figure 2–55. Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables or disables the clock to reduce power consumption. Table 2–16 lists the global and regional clock features. Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. GCLK networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–54 shows the 12 dedicated CLK pins driving global clock networks. Table 2–16. Global and Regional Clock Features Feature Global Clocks Regional Clocks Number per device 16 32 Number available per quadrant 16 8 Sources Clock pins, PLL outputs, core routings, inter-transceiver clocks Clock pins, PLL outputs, core routings, inter-transceiver clocks Dynamic clock source selection v — Dynamic enable/disable vv |
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