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EP1AGX50CF484I6N Datasheet(PDF) 44 Page - Altera Corporation |
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EP1AGX50CF484I6N Datasheet(HTML) 44 Page - Altera Corporation |
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44 / 234 page  2–38 Chapter 2: Arria GX Architecture Adaptive Logic Modules Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in Figure 2–34, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. While operating in arithmetic mode, the ALM can support simultaneous use of the adder’s carry output along with combinational logic outputs. In this operation, adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–35. The equation for this example is: To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data ‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the syncload signal is deasserted and ‘X’ drives the data port of the registers. Figure 2–34. ALM in Arithmetic Mode dataf0 datae0 carry_in carry_out dataa datab datac datad datae1 dataf1 DQ DQ To general or local routing To general or local routing reg0 reg1 To general or local routing To general or local routing 4-Input LUT 4-Input LUT 4-Input LUT 4-Input LUT adder1 adder0 Equation 2–1. R= (X < Y) ? Y : X |
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