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EP1AGX50CF780C6N Datasheet(PDF) 89 Page - Altera Corporation |
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EP1AGX50CF780C6N Datasheet(HTML) 89 Page - Altera Corporation |
89 / 234 page Chapter 2: Arria GX Architecture 2–83 I/O Structure © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 Figure 2–68 shows how a row I/O block connects to the logic array. Figure 2–68. Row I/O Block Connection to the Interconnect Note to Figure 2–68: (1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0]. 32 R4 & R24 Interconnects C4 Interconnect I/O Block Local Interconnect 32 Data & Control Signals from Logic Array (1) io_dataina[3..0] io_datainb[3..0] io_clk[7:0] Horizontal I/O Block Contains up to Four IOEs Direct Link Interconnect to Adjacent LAB Direct Link Interconnect to Adjacent LAB LAB Local Interconnect LAB Horizontal I/O Block |
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