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PIC16C432 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC16C432 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 106 page  2002 Microchip Technology Inc. Preliminary DS41140B-page 9 PIC16C432 TABLE 3-1: SPECIAL REGISTERS FOR THE PIC16C432 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other RESETS(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 16 01h TMR0 Timer0 Module’s Register xxxx xxxx 27 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 15 03h STATUS IRP(2) RP1(2) RP0 TO PD ZDC C 0001 1xxx 10 04h FSR Indirect data memory address pointer xxxx xxxx 16 05h PORTA — — — RA4 RA3 RA2 LINRX RA0 ---x 0000 17 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 20 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 15 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 12 0Ch PIR1 — CMIF — — — — — — -0-- ---- 13 0Dh-1Eh — Unimplemented — — 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 33 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 16 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 11 82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 15 83h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 10 84h FSR Indirect data memory address pointer xxxx xxxx 16 85h TRISA — — — TRISA4 TRISA3 TRISA2 TLINRX(3) TRISA0 ---1 1111 17 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 20 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 15 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 12 8Ch PIE1 — CMIE — — — — — — -0-- ---- 13 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOD ---- --0x 14 8Fh-9Eh — Unimplemented — — 90h LININTF — — — — — LINTX — LINVDD ---- -1-1 23 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 41 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) RESETS include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. 2: IRP & RPI bits are reserved; always maintain these bits clear. 3: TLINRX must set to ‘1’ at all times. |
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Similar Description - PIC16C432 |
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