TDA9882 datasheet(9/45 Pages) NXP

Part #	TDA9882

Description	Alignment-free multistandard vision and QSS FM sound IF PLL demodulator

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Manufacturer	NXP [NXP Semiconductors]

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9397 750 13507

Product data sheet

Rev. 01 — 16 November 2004

9 of 45

Philips Semiconductors

TDA9882

Multistandard vision and QSS FM sound IF PLL demodulator

The in-window and out-window control at the FM PLL can additionally be used to mute the

audio stage (if auto mute is selected via pins SIF1 and SIF2); see Table 6.

The principle working of the digital acquisition help circuit is as follows: The PLL VCO

output is connected to a downcounter which has a predeﬁned start value (standard

dependent). The VCO frequency clocks the downcounter for a ﬁxed gate time. Thereafter,

the downcounter stop value is analyzed. In the event that the stop value is higher (lower)

than the expected value range, the VCO frequency will be lower (higher) than the required

lock-in window frequency range. A positive (negative) control current is injected into the

PLL loop ﬁlter which causes the VCO frequency to be increased (decreased) and a new

counting cycle starts.

The gate time as well as the control logic of the acquisition help circuit is dependent on the

precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as

well as connecting this input via a serial capacitor to an external reference frequency e.g.

the tuning system oscillator.

The AFC signal is derived from the corresponding downcounter stop value after a

counting cycle. The last four bits are latched and the digital-to-analog converted value is

given as current at pin AFC.

8.7 Video demodulator and ampliﬁer

The video demodulator is realized by a multiplier which is designed for low distortion and

large bandwidth. The VIF signal is multiplied with the ‘in phase’ signal of the VIF PLL

VCO.

The demodulator output signal is fed into the video preampliﬁer via a level shift stage with

integrated low-pass ﬁlter to achieve carrier harmonics attenuation.

The output signal of the preampliﬁer is fed to the VIF AGC detector (see Section 8.3) and

also fed internally to the integrated sound carrier trap; see Section 8.8. The differential

trap output signal is converted and ampliﬁed by the following postampliﬁer. The video

output level at pin CVBS is 2 V (p-p).

Noise clipping is provided.

8.8 Sound carrier trap

The sound carrier trap consists of a reference ﬁlter, a phase detector and the sound trap

itself.

A sound carrier reference signal is fed into the reference low-pass ﬁlter and is shifted by

nominal 90 degrees. The phase detector compares the original reference signal with the

signal shifted by the reference ﬁlter and produces a DC voltage by charging or discharging

an integrated capacitor with a current proportional to the phase difference between both

signals, respectively to the frequency error of the integrated ﬁlters. The DC voltage

controls the frequency position of the reference ﬁlter and the sound trap. Thus the

accurate frequency position for the different standards is set by the sound carrier

reference signal.

The sound trap itself is constructed of three separate traps to realize sufﬁcient

suppression of the ﬁrst and second sound carrier.

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