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MB90488BPMC Datasheet(PDF) 18 Page - Fujitsu Component Limited. |
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MB90488BPMC Datasheet(HTML) 18 Page - Fujitsu Component Limited. |
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18 / 124 page  MB90480B/485B Series 18 DS07-13722-11E ■ BLOCK DIAGRAM RAM ROM μDMAC 8 2 X0, X1, RST X0A, X1A MD2, MD1, MD0 SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 PPG0 to PPG5 88 8 8 8 8 8 8 8 P00 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P77 P80 P87 8 P90 P97 4 PA0 PA3 IN0, IN1 CS0 to CS3 TIN0 TOT0 IRQ0 to IRQ7 8 SCL SDA EXTC MT00 MT01 PWC0 PWC1 PWC2 Clock control Circuit CPU F2MC16LX series core Interrupt controller 8/16-bit PPG 8/16-bit up/down counter/timer μPG Chip select Input/output timer 16-bit input capture × 2 channels 16-bit output compare × 6 channels 16-bit free-run timer 16-bit reload timer I2C interface External interrupt UART Extended I/O serial interface × 2 channels A/D converter ( 8/10-bit ) PWC × 3 channels I/O port to to to to to to to to to to to Communication prescaler : Only MB90485B series OUT0 to OUT5 P00 to P07 (8 pins) : with an input pull-up resistance setting register. P10 to P17 (8 pins) : with an input pull-up resistance setting register. P40 to P47 (8 pins) : with an open drain setting register. P70 to P77 (8 pins) : with an open drain setting register. MB90485B series only • I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . • P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ μPG/I2C become CMOS input. Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. |
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