DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 2. Register Map

DATA

ADDRESS

B7

B6

B5

B4

B3

B2

B1

B0

FUNCTION

RANGE

1FFFF

10 Year

Year

Year

00-99

1FFFE

X

X

X

10 Month

Month

Month

01-12

1FFFD

X

X

10 Date

Date

Date

01-31

1FFFC

BF

FT

X

X

X

Day

Day

01-07

1FFFB

X

X

10 Hour

Hour

Hour

00-23

1FFFA

X

10 Minutes

Minutes

Minutes

00-59

1FFF9

OSC

10 Seconds

Seconds

Seconds

00-59

1FFF8

W

R

10 Century

Century

Century

00-39

OSC = Stop Bit

R = Read Bit

FT = Frequency Test

W = Write Bit

X = See Note

BF = Battery Flag

Note: All indicated “X” bits are not used but must be set to “0” during a write cycle to ensure proper clock

operation.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1746 is in the read mode whenever

OE (output enable) is low, WE (write enable) is high, and CE

(chip enable) is low. The device architecture allows ripple-through access to any of the address locations

stable, providing that the

CE and OE access times and states are satisfied. If CE or OE access times and

are changed while

but will then go indeterminate until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1746 is in the write mode whenever

WE, and CE are in their active state. The start of a write is

referenced to the latter occurring transition of

WE, or CE. The addresses must be held valid throughout

the cycle.

CE or WE must return inactive for a minimum of t

typical application, the

OE signal will be high during a write cycle. However, OE can be active provided

that care is taken with the data bus to avoid bus contention. If

OE is low prior to WE transitioning low the

data bus can become active with read data defined by the address inputs. A low transition on

WE will