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DS1556W-120+ Datasheet(PDF) 4 Page - Maxim Integrated Products |
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DS1556W-120+ Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 18 page DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM 4 of 18 Figure 1. Block Diagram Table 1. Operating Modes VCC CE OE WE DQ0–DQ7 MODE POWER VIH X X High-Z Deselect Standby VIL X VIL DIN Write Active VIL VIL VIH DOUT Read Active VCC > VPF VIL VIH VIH High-Z Read Active VSO < VCC <VPF X X X High-Z Deselect CMOS Standby VCC <VSO < VPF X X X High-Z Data Retention Battery Current DATA READ MODE The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before t AA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. DATA WRITE MODE The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of t WR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In Maxim DS1556 |
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