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DS1338C-33 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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DS1338C-33 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 16 page DS1338 I 2C RTC with 56-Byte NV RAM 8 of 16 OPERATION The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below V PF, the internal clock registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The oscillator and timekeeping functions are maintained from the VBAT source until VCC is returned to nominal levels. The block diagram (Figure 3) shows the main elements of the DS1338. An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within 1 second. POWER CONTROL The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1. Table 1. Power Control SUPPLY CONDITION READ/WRITE ACCESS POWERED BY VCC < VPF, VCC < VBAT No VBAT VCC < VPF, VCC > VBAT No VCC VCC > VPF, VCC < VBAT Yes VCC VCC > VPF, VCC > VBAT Yes VCC OSCILLATOR CIRCUIT The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics. Table 2. Crystal Specifications* PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz Series Resistance ESR 50 k Load Capacitance CL 12.5 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. |
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Similar Description - DS1338C-33 |
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