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DS3153 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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DS3153 Datasheet(HTML) 10 Page - Maxim Integrated Products |
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10 / 61 page  DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 10 of 61 4. PIN DESCRIPTIONS Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes NAME TYPE FUNCTION HARDWARE MODE CPU BUS MODE TRANSMITTER TCLKn I Transmitter Clock Active Active TPOSn/TDATn I Transmitter Positive AMI/Transmitter Data Active Active TNEGn I Transmitter Negative AMI Active Active TXPn, TXNn O Transmitter Analog Outputs Active Active TTSn I Transmitter Tri-State Enable Active Active TDMn O Transmitter Driver Monitor Output Active Active TDSAn, TDSBn I Transmitter Data Select Active TLBOn I Transmitter Line Build-Out Enable Active TJAn I Transmitter Jitter Attenuator Enable Active RECEIVER RXPn, RXNn I Receiver Analog Inputs Active Active RCLKn O Receiver Clock Active Active RPOSn/RDATn O Receiver Positive AMI/Receiver Data Active Active RNEGn/RLCVn O Receiver Negative AMI/Line-Code Violation Active Active RTSn I Receiver Tri-State Enable Active Active RLOSn O Receiver LOS Output Active Active RMONn I Receiver Monitor Enable Active RJAn I Receiver Jitter Attenuator Enable Active GLOBAL HIZ I High-Z Enable Active Active RST I Reset Enable Active Active HW I Hardwired Mode Enable Active Active T3MCLK I T3 Master Clock (44.736MHz ±20ppm) Active Active E3MCLK I E3 Master Clock (34.368MHz ±20ppm) Active Active STMCLK I STS-1 Master Clock (51.840MHz ±20ppm) Active Active PRBSn O PRBS Detector Output Active Active LLBn, RLBn I Local Loopback, Remote Loopback Select Active E3Mn, STSn I E3 Mode Enable, STS-1 Mode Enable Active RBIN I Receiver Binary Interface Enable Active TBIN I Transmitter Binary Interface Enable Active RCINV I Receiver Clock Invert Active TCINV I Transmitter Clock Invert Active MOT I Motorola CPU Bus Enable Active ALE I Address Latch Enable Active CS I Chip Select Active WR / R/W I Write Enable / Read/Write Select Active RD/DS I Read Enable/Data Strobe Active A[5:0] I Address Bus Active D[7:0] I/O Data Bus Active INT O Interrupt Output Active Note: In CPU bus mode, status/control pins are replaced by register bits. See Register Map in Section 5. For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc. |
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