 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS2156G Datasheet(PDF) 2 Page - Maxim Integrated Products |
|
||||||||||||||||||||||||||||||
DS2156G Datasheet(HTML) 2 Page - Maxim Integrated Products |
|
|
2 / 265 page  DS2156 2 of 265 TABLE OF CONTENTS 1. MAIN FEATURES............................................................................................................ 9 2. DETAILED DESCRIPTION............................................................................................ 12 2.1 BLOCK DIAGRAM........................................................................................................................ 14 3. PIN FUNCTION DESCRIPTION .................................................................................... 20 3.1 TDM BACKPLANE ...................................................................................................................... 20 3.1.1 Transmit Side .......................................................................................................................................20 3.1.2 Receive Side ........................................................................................................................................23 3.2 UTOPIA BUS ............................................................................................................................ 26 3.2.1 Receive Side ........................................................................................................................................26 3.2.2 Transmit Side .......................................................................................................................................27 3.3 PARALLEL CONTROL PORT PINS ................................................................................................ 28 3.4 EXTENDED SYSTEM INFORMATION BUS ...................................................................................... 29 3.5 USER OUTPUT PORT PINS ......................................................................................................... 30 3.6 JTAG TEST ACCESS PORT PINS................................................................................................ 31 3.7 LINE INTERFACE PINS ................................................................................................................ 32 3.8 SUPPLY PINS............................................................................................................................. 33 3.9 L AND G PACKAGE PINOUT ........................................................................................................ 34 3.10 10MM CSBGA PIN CONFIGURATION .......................................................................................... 38 4. PARALLEL PORT ......................................................................................................... 39 4.1 REGISTER MAP.......................................................................................................................... 39 4.2 UTOPIA BUS REGISTERS.......................................................................................................... 45 5. SPECIAL PER-CHANNEL REGISTER OPERATION ................................................... 46 6. PROGRAMMING MODEL ............................................................................................. 48 6.1 POWER-UP SEQUENCE.............................................................................................................. 49 6.1.1 Master Mode Register..........................................................................................................................49 6.2 INTERRUPT HANDLING ............................................................................................................... 50 6.3 STATUS REGISTERS................................................................................................................... 50 6.4 INFORMATION REGISTERS.......................................................................................................... 51 6.5 INTERRUPT INFORMATION REGISTERS ........................................................................................ 51 7. CLOCK MAP.................................................................................................................. 52 8. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS ........................... 53 8.1 T1 CONTROL REGISTERS........................................................................................................... 53 8.2 T1 TRANSMIT TRANSPARENCY ................................................................................................... 58 8.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ..................................................................... 58 8.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION ......................................................... 59 9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS........................... 62 9.1 E1 CONTROL REGISTERS .......................................................................................................... 62 9.2 AUTOMATIC ALARM GENERATION ............................................................................................... 66 9.3 E1 INFORMATION REGISTERS .................................................................................................... 67 10. COMMON CONTROL AND STATUS REGISTERS ...................................................... 69 10.1 T1/E1 STATUS REGISTERS ........................................................................................................ 70 11. I/O PIN CONFIGURATION OPTIONS ........................................................................... 76 12. LOOPBACK CONFIGURATION.................................................................................... 78 12.1 PER-CHANNEL LOOPBACK ......................................................................................................... 80 13. ERROR COUNT REGISTERS ....................................................................................... 82 13.1 LINE-CODE VIOLATION COUNT REGISTER (LCVCR) ................................................................... 83 13.1.1 T1 Operation ........................................................................................................................................83 13.1.2 E1 Operation ........................................................................................................................................83 13.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) .................................................................. 85 |
Similar Part No. - DS2156G |
|
Similar Description - DS2156G |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
