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QLX4600LIQT7 Datasheet(PDF) 13 Page - Intersil Corporation |
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QLX4600LIQT7 Datasheet(HTML) 13 Page - Intersil Corporation |
13 / 23 page 13 FN6981.1 November 19, 2009 Line Silence/Electrical Idle/Quiescent Mode Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The QLx4600-SL30 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity- enhancing benefits of limiting amplification during active data transmission. Line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the current at the DT pin. When the amplitude falls below the threshold, the output driver stages are muted and held at their nominal common mode voltage1. LOS Indicator Pins LOS[k] are used to output the state of the muting circuitry to serve as a loss of signal indicator for channel k. This signal is directly derived from the muting signal off the DT-threshold signal detector output. The LOS signal goes ‘HIGH’ when the power signal is below the DT threshold and ‘LOW’ when the power goes above the DT threshold. This feature is meant to be used in optical systems (e.g. QSFP) where there are no quiescent or electrical-idle states. In these cases, the DT threshold is used to determine the sensitivity of the LOS indicator. Applications Information Several aspects of the QLx4600-SL30 are capable of being dynamically managed by a system controller to provide maximum flexibility and optimum performance. These functions are controlled by interfacing to the highlighted pins in Figure 26. The specific procedures for controlling these aspects of the QLx4600-SL30 are the focus of this section. Equalization Boost Level Channel equalization for the QLx4600-SL30 can be individually set to either (a) one of 18 levels through the DC voltages on external control pins or (b) one of 32 levels via a set of registers programmed by a low speed serial bus. The pins used to control the boost level are highlighted in Figure 26. Descriptions of these pins are listed in Table 1. Please refer to “Pin Descriptions” on page 3 for descriptions of all other pins on the QLx4600-SL30. FIGURE 24. CML INPUT EQUIVALENT CIRCUIT FOR THE QLx4600-S30 FIGURE 25. CML OUTPUT EQUIVALENT CIRCUIT FOR THE QLx4600-S30 NOTE: The load value of 52Ω is used to internally match SDD22 for a characteristic impedance of 50Ω. IN[k] P IN[k] N Buffer VDD 50Ω 50Ω VDD 52Ω 52Ω OUT[k] P OUT[k] N 1. The output common mode voltage remains constant during both active data transmission and output muting modes. 44 40 41 42 43 1 32 10 9 8 7 6 5 4 3 2 38 24 25 26 27 28 29 30 31 23 20 19 18 17 16 11 12 33 14 13 34 45 39 46 22 21 35 36 15 37 IN1[P] IN1[N] IN2[P] IN2[N] IN3[P] IN3[N] IN4[P] IN4[N] OUT1[P] OUT1[N] OUT2[P] OUT2[N] OUT3[P] OUT3[N] OUT4[P] OUT4[N] DT Quellan QLx4600-SL30 46-Lead QFN 7mm x 4mm 0.4mm Pitch Exposed Pad (GND) GND LOS1 LOS4 MODE LOS2 LOS3 BGREF VDD VDD VDD VDD VDD VDD FIGURE 26. PIN DIAGRAM HIGHLIGHTING PINS USED FOR DYNAMIC CONTROL OF THE QLx4600- SL30 QLx4600-SL30 |
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