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EP1AGX35EF780C6N Datasheet(PDF) 96 Page - Altera Corporation |
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EP1AGX35EF780C6N Datasheet(HTML) 96 Page - Altera Corporation |
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96 / 234 page  2–90 Chapter 2: Arria GX Architecture I/O Structure Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock to meet DDR SDRAM timing requirements. External RAM Interfacing In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces, including DDR, DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top (Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number of DQ and DQS buses that are supported per device. A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. Figure 2–76. Output Timing Diagram in DDR Mode From Internal Registers DDR output CLK B1 A1 B2 A2 B3 A3 B4 A4 A2 A1 A3 A4 B1 B2 B3 B4 Table 2–23. DQS and DQ Bus Mode Support (Note 1) Device Package Number of ×4 Groups Number of ×8/×9 Groups Number of ×16/×18 Groups Number of ×32/×36 Groups EP1AGX20 484-pin FineLine BGA 2 0 0 0 EP1AGX35 484-pin FineLine BGA 2 0 0 0 780-pin FineLine BGA 18 8 4 0 EP1AGX50/60 484-pin FineLine BGA 2 0 0 0 780-pin FineLine BGA 18 8 4 0 1,152-pin FineLine BGA 36 18 8 4 EP1AGX90 1,152-pin FineLine BGA 36 18 8 4 Note to Table 2–23: (1) Numbers are preliminary until devices are available. |
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