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EP1AGX Datasheet(PDF) 90 Page - Altera Corporation |
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EP1AGX Datasheet(HTML) 90 Page - Altera Corporation |
90 / 234 page 2–84 Chapter 2: Arria GX Architecture I/O Structure Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Figure 2–69 shows how a column I/O block connects to the logic array. There are 32 control and data signals that feed each row or column I/O block. These control and data signals are driven from the logic array. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from global or regional clocks (refer to “PLLs and Clock Networks” on page 2–66). Figure 2–69. Column I/O Block Connection to the Interconnect Note to Figure 2–69: (1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0]. 32 Data & Control Signals from Logic Array (1) Vertical I/O Block Contains up to Four IOEs I/O Block Local Interconnect IO_dataina[3..0] IO_datainb[3..0] R4 & R24 Interconnects LAB Local Interconnect C4 & C16 Interconnects 32 LAB LAB LAB io_clk[7..0] Vertical I/O Block |
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